1. Field of the Invention
The present invention relates to solid state devices that utilize a thin layer of silicon dioxide as a dielectric.
2. Description of the Prior Art
Numerous applications exist in the semiconductor art for thin layers (i.e., &lt;25 nanometers) of silicon dioxide grown on deposited silicon. For example, in a switched-capacitor filter or a dynamic random access memory, a capacitor dielectric may be formed by first depositing a layer of polycrystalline silicon ("polysilicon", or "poly"), which is doped with an impurity to form a first conductive plate of the capacitor. Depending on the doping and deposition conditions, polysilicon as deposited comprises grains of single-crystal silicon having a grain size (diameter) of typically from about 50 to 200 nanometers. The doped polysilicon is then heated in an oxygen ambient for a period of about one-half hour, in order to oxidize the surface, thereby forming a dielectric layer of SiO.sub.2. An additional layer of doped polysilicon may then be deposited on the SiO.sub.2 dielectric layer, in order to form the second capacitor plate. Prior to forming this second plate, a silicon nitride layer may optionally be formed by growth or deposition on the silicon dioxide layer, producing a "dual dielectric" capacitor. In a dynamic memory, the capacitor may extend over the adjoining access transistor in the "stacked capacitor" structure, or may be located in a trench alongside the access transistor, with other configurations being possible. The elevated temperature of the oxidizing process, and subsequent heat treatments involved in the other process steps, typically cause the polysilicon grain sizes (in the unoxidized portions) to increase to perhaps 100 to 1000 nanometers.
A very important criterion of the quality of the dielectric layer is its breakdown voltage for a given dielectric thickness. That is, it is desirable to use as thin a dielectric as possible, in order to maximize the capacitance per unit area, while obtaining the required breakdown voltage to operate without failure. It is generally known in the art that the breakdown voltage of oxidized polysilicon is less than the breakdown voltage of oxidized single-crystal silicon of comparable thickness. Therefore, a thicker layer of SiO.sub.2 is used when it is formed from polysilicon, as when formed from single-crystal silicon (e.g., a substrate), to obtain a comparable breakdown voltage. It is known that furnace oxidation of in-situ doped polysilicon deposited at 600 degrees C. produces a higher breakdown voltage than when deposited at 640 degrees C.; see "Properties of Thermal Oxides Grown on Phosphorus in-situ Doped Polysilicon", M. Steinheim et al, Journal of the Electrochemical Society, Vol. 130, pp. 1735-1740 (1983). In addition, it is known that silicon tends to deposit in the amorphous state at deposition temperatures below about 590 degrees C. It has been proposed to deposit silicon in the amorphous state, and then oxidize it; see "Characterization of Thermally Oxidized n.sup.+ Polycrystalline Silicon", L. Faraone et al, IEEE Transactions on Electron Devices, Vol. ED-32, pp. 577-583 (1985). However, the doping techniques utilized therein resulted in at least a surface portion of the silicon converting to the polycrystalline state prior to, or during, oxidation.
Another application of SiO.sub.2 layers grown on deposited polysilicon is for the top dielectric of the "floating gate" in electrically erasable programmable read-only-memories (EEPROMs); see, for example, U.S. Pat. No. 4,544,418. That patent also discloses rapidly oxidizing the (single crystal) substrate in order to form the thin gate oxide layer of such a device. In general, it is also desirable to be able to form the top dielectric from as thin an oxide as possible, to minimize the voltage required to write data into the device. It is also known to use oxidized polysilicon as the gate dielectric of an insulated gate field effect transistor. In that case also, smaller device geometrics require thinner gate oxides that still obtain a satisfactory breakdown voltage.